AD9361 设置中心频率

2.2G

//************************************************************
// FDD RX,TX Synth Frequency: 2200.000000,2200.000000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************
			12'd864 :cmd_data={1'b1,10'h23a,8'h4a};// Set VCO Output level[3:0]
			12'd865 :cmd_data={1'b1,10'h239,8'hc1};// Set Init ALC Value[3:0] and VCO Varactor[3:0]
			12'd866 :cmd_data={1'b1,10'h242,8'h0e};// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
			12'd867 :cmd_data={1'b1,10'h238,8'h78};// Set VCO Cal Offset[3:0]
			12'd868 :cmd_data={1'b1,10'h245,8'h00};// Set VCO Cal Ref Tcf[2:0]
			12'd869 :cmd_data={1'b1,10'h251,8'h0b};// Set VCO Varactor Reference[3:0]
			12'd870 :cmd_data={1'b1,10'h250,8'h70};// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
			12'd871 :cmd_data={1'b1,10'h23b,8'h8e};// Set Synth Loop Filter charge pump current (Icp)
			12'd872 :cmd_data={1'b1,10'h23e,8'hd4};// Set Synth Loop Filter C2 and C1
			12'd873 :cmd_data={1'b1,10'h23f,8'hdf};// Set Synth Loop Filter  R1 and C3
			12'd874 :cmd_data={1'b1,10'h240,8'h09};// Set Synth Loop Filter R3
//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************
			12'd875	:cmd_data={1'b1,10'h27a,8'h4a};// Set VCO Output level[3:0]
			12'd876	:cmd_data={1'b1,10'h279,8'hc1};// Set Init ALC Value[3:0] and VCO Varactor[3:0]
			12'd877	:cmd_data={1'b1,10'h282,8'h0e};// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
			12'd878	:cmd_data={1'b1,10'h278,8'h78};// Set VCO Cal Offset[3:0]
			12'd879	:cmd_data={1'b1,10'h285,8'h00};// Set VCO Cal Ref Tcf[2:0]
			12'd880	:cmd_data={1'b1,10'h291,8'h0b};// Set VCO Varactor Reference[3:0]
			12'd881	:cmd_data={1'b1,10'h290,8'h70};// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
			12'd882	:cmd_data={1'b1,10'h27b,8'h8e};// Set Synth Loop Filter charge pump current (Icp)
			12'd883	:cmd_data={1'b1,10'h27e,8'hd4};// Set Synth Loop Filter C2 and C1
			12'd884	:cmd_data={1'b1,10'h27f,8'hdf};// Set Synth Loop Filter  R1 and C3
			12'd885	:cmd_data={1'b1,10'h280,8'h09};// Set Synth Loop Filter R3
//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************
			12'd886	:cmd_data={1'b1,10'h233,8'h00};// Write Rx Synth Fractional Freq Word[7:0]
			12'd887	:cmd_data={1'b1,10'h234,8'h00};// Write Rx Synth Fractional Freq Word[15:8]
			12'd888	:cmd_data={1'b1,10'h235,8'h00};// Write Rx Synth Fractional Freq Word[22:16]
			12'd889	:cmd_data={1'b1,10'h232,8'h00};// Write Rx Synth Integer Freq Word[10:8]
			12'd890	:cmd_data={1'b1,10'h231,8'h6e};// Write Rx Synth Integer Freq Word[7:0]   由8C改为91
			12'd891	:cmd_data={1'b1,10'h005,8'h11};// Set LO divider setting
			12'd892	:cmd_data={1'b1,10'h273,8'h00};// Write Tx Synth Fractional Freq Word[7:0]
			12'd893	:cmd_data={1'b1,10'h274,8'h00};// Write Tx Synth Fractional Freq Word[15:8]
			12'd894	:cmd_data={1'b1,10'h275,8'h00};// Write Tx Synth Fractional Freq Word[22:16]
			12'd895	:cmd_data={1'b1,10'h272,8'h00};// Write Tx Synth Integer Freq Word[10:8]
			12'd896	:cmd_data={1'b1,10'h271,8'h6e};// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) 由8C改为91
			12'd897	:cmd_data={1'b1,10'h005,8'h11};// Set LO divider setting
			12'd898	:cmd_data={1'b0,10'h247,8'h00};// Check RX RF PLL lock status (0x247[1]==1 is locked)
			12'd899	:cmd_data={1'b0,10'h287,8'h00};// Check TX RF PLL lock status (0x287[1]==1 is locked)

1.4G

//************************************************************
// FDD RX,TX Synth Frequency: 1400.000000,1400.000000 MHz
//************************************************************
//************************************************************
// Setup Rx Frequency-Dependent Syntheisizer Registers
//************************************************************
			12'd864 :cmd_data={1'b1,10'h23a,8'h4a};// Set VCO Output level[3:0]
			12'd865 :cmd_data={1'b1,10'h239,8'hc0};// Set Init ALC Value[3:0] and VCO Varactor[3:0]
			12'd866 :cmd_data={1'b1,10'h242,8'h04};// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
			12'd867 :cmd_data={1'b1,10'h238,8'h70};// Set VCO Cal Offset[3:0]
			12'd868 :cmd_data={1'b1,10'h245,8'h00};// Set VCO Cal Ref Tcf[2:0]
			12'd869 :cmd_data={1'b1,10'h251,8'h08};// Set VCO Varactor Reference[3:0]
			12'd870 :cmd_data={1'b1,10'h250,8'h70};// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
			12'd871 :cmd_data={1'b1,10'h23b,8'h8d};// Set Synth Loop Filter charge pump current (Icp)
			12'd872 :cmd_data={1'b1,10'h23e,8'hd4};// Set Synth Loop Filter C2 and C1
			12'd873 :cmd_data={1'b1,10'h23f,8'hdf};// Set Synth Loop Filter  R1 and C3
			12'd874 :cmd_data={1'b1,10'h240,8'h09};// Set Synth Loop Filter R3
//************************************************************
// Setup Tx Frequency-Dependent Syntheisizer Registers
//************************************************************
			12'd875	:cmd_data={1'b1,10'h27a,8'h4a};// Set VCO Output level[3:0]
			12'd876	:cmd_data={1'b1,10'h279,8'hc0};// Set Init ALC Value[3:0] and VCO Varactor[3:0]
			12'd877	:cmd_data={1'b1,10'h282,8'h04};// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
			12'd878	:cmd_data={1'b1,10'h278,8'h70};// Set VCO Cal Offset[3:0]
			12'd879	:cmd_data={1'b1,10'h285,8'h00};// Set VCO Cal Ref Tcf[2:0]
			12'd880	:cmd_data={1'b1,10'h291,8'h08};// Set VCO Varactor Reference[3:0]
			12'd881	:cmd_data={1'b1,10'h290,8'h70};// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
			12'd882	:cmd_data={1'b1,10'h27b,8'h8d};// Set Synth Loop Filter charge pump current (Icp)
			12'd883	:cmd_data={1'b1,10'h27e,8'hd4};// Set Synth Loop Filter C2 and C1
			12'd884	:cmd_data={1'b1,10'h27f,8'hdf};// Set Synth Loop Filter  R1 and C3
			12'd885	:cmd_data={1'b1,10'h280,8'h09};// Set Synth Loop Filter R3
//************************************************************
// Write Rx and Tx Frequency Words
//************************************************************
			12'd886	:cmd_data={1'b1,10'h233,8'h00};// Write Rx Synth Fractional Freq Word[7:0]
			12'd887	:cmd_data={1'b1,10'h234,8'h00};// Write Rx Synth Fractional Freq Word[15:8]
			12'd888	:cmd_data={1'b1,10'h235,8'h00};// Write Rx Synth Fractional Freq Word[22:16]
			12'd889	:cmd_data={1'b1,10'h232,8'h00};// Write Rx Synth Integer Freq Word[10:8]
			12'd890	:cmd_data={1'b1,10'h231,8'h8c};// Write Rx Synth Integer Freq Word[7:0]
			12'd891	:cmd_data={1'b1,10'h005,8'h02};// Set LO divider setting
			12'd892	:cmd_data={1'b1,10'h273,8'h00};// Write Tx Synth Fractional Freq Word[7:0]
			12'd893	:cmd_data={1'b1,10'h274,8'h00};// Write Tx Synth Fractional Freq Word[15:8]
			12'd894	:cmd_data={1'b1,10'h275,8'h00};// Write Tx Synth Fractional Freq Word[22:16]
			12'd895	:cmd_data={1'b1,10'h272,8'h00};// Write Tx Synth Integer Freq Word[10:8]
			12'd896	:cmd_data={1'b1,10'h271,8'h8c};// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
			12'd897	:cmd_data={1'b1,10'h005,8'h22};// Set LO divider setting
			12'd898	:cmd_data={1'b0,10'h247,8'h00};// Check RX RF PLL lock status (0x247[1]==1 is locked)
			12'd899	:cmd_data={1'b0,10'h287,8'h00};// Check TX RF PLL lock status (0x287[1]==1 is locked)