EDA期末复习

仅用于21级计算机科学与技术班。微电子班，微产班，电子信息班，物联网班均不适用。

题目类型及分值分布

1.选择10个，一个2分

2.名词解释5个，一个2分（去年的五个是：CPLD，ASIC,LUT,EDA,RTL）

3.VHLD程序填空3个，一个10分（依次是：D触发器，4选1多路开关，移位寄存器，）

4.VHDL程序设计4个，一个10分（依次是完成逻辑设计：Y=AB+C，根据逻辑真值表完成设计，设计分频器，对信号十分频，描述状态机）

根据以上内容大胆猜测：选择和名词解释课本上基本都在前两章，自己翻书。大题极有可能只是改变数值，但是不改变主要思路、题型和代码。?

那么目前需要做的任务是：看懂VHDL代码，记住（打印）以上内容的主要写法。

笔者将从以下两个部分给大家提供帮助：

看懂VHDL代码

VHDL代码的组成部分：

与c语言类似，头文件+实体+构造体

头文件

跟C语言一样，在我们考试的时候可以直接照搬

?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_UNSIGNED.ALL;

头文件多写问题不大，我们课本上没有比以上的多了，开头三行就写这个

实体（ENTITY）

这个东西的作用有些类似C语言的输入输出

实体关键字  实体名  IS
通用属性关键字(
               参数名 : 参数类型 := 参数值；
               )；
端口关键字(
           端口名:端口信号模式:数据类型；
           …
           …
          )
END 实体名;

ENTITY entity_name IS

             
PORT  (
       a,b,c,d:IN BIT;
             x:OUT BIT;
      )
END entity_name;

IN和OUT是输入和输出，bit是数据类型中的整数型。

ENTITY和PORT这些基本是固定不变的不用管

所以以上这一串的作用类似：

cin>>a>>b>>c>>d;
cout<<x;

构造体（ARCHITECTURE）

类似C语言的函数，这部分内容就比较多，里面填的东西随功能的变化也各有不同，不过有具体的格式：

ARCHITECTURE 结构体名 OF 实体名	IS
        [声明语句]
	BEGIN
	功能描述语句;
END	结构体名;

?记住（打印）以下经典例子：

1.状态机

library ieee;
use ieee.std_logic_1164.all;

entity FSM is
  port (
    clk : in std_logic;
    reset : in std_logic;
    input : in std_logic;
    output : out std_logic_vector(1 downto 0)
  );
end entity;

architecture Behavioral of FSM is
  type StateType is (S0, S1, S2, S3);
  signal currentState, nextState : StateType;

begin
  process (clk, reset)
  begin
    if reset = '1' then
      currentState <= S0;   -- 初始状态为 S0
    elsif clk'event and clk='1' then
      currentState <= nextState;  -- 根据下一个状态更新当前状态
    end if;
  end process;

  process (currentState, input)
  begin
    case currentState is
      when S0 =>
        if input = '0' then
          nextState <= S1;
        elsif input = '1' then
          nextState <= S3;
        else
          nextState <= S0;
        end if;

      when S1 =>
        if input = '0' then
          nextState <= S2;
        elsif input = '1' then
          nextState <= S0;
        else
          nextState <= S1;
        end if;

      when S2 =>
        if input = '0' then
          nextState <= S3;
        elsif input = '1' then
          nextState <= S1;
        else
          nextState <= S2;
        end if;

      when S3 =>
        if input = '0' then
          nextState <= S0;
        elsif input = '1' then
          nextState <= S2;
        else
          nextState <= S3;
        end if;

      when others =>
        nextState <= S0;
    end case;
  end process;

  process (currentState)
  begin
    case currentState is
      when S0 =>
        output <= "00";

      when S1 =>
        output <= "01";

      when S2 =>
        output <= "10";

      when S3 =>
        output <= "11";

      when others =>
        output <= "00";
    end case;
  end process;

end architecture;

2.完成逻辑设计：Y=AB+C

library ieee;
use ieee.std_logic_1164.all;

entity LogicDesign is
  port (
    A, B, C : in std_logic;
    Y : out std_logic
  );
end entity;

architecture Behavioral of LogicDesign is
begin
  process (A, B, C)
  begin
    if (A = '1' and B = '1') or C = '1' then
      Y <= '1';
    else
      Y <= '0';
    end if;
  end process;

end architecture;

3.?根据逻辑真值表完成设计（2-4译码器）

library ieee;
use ieee.std_logic_1164.all;

entity Decoder2to4 is
  port (
    A, B : in std_logic;
    Y1, Y2, Y3, Y4 : out std_logic
  );
end entity;

architecture Behavioral of Decoder2to4 is
begin
  process (A, B)
  begin
    case (A, B) is
      when ('0', '0') =>
        Y1 <= '1';
        Y2 <= '0';
        Y3 <= '0';
        Y4 <= '0';

      when ('0', '1') =>
        Y1 <= '0';
        Y2 <= '1';
        Y3 <= '0';
        Y4 <= '0';

      when ('1', '0') =>
        Y1 <= '0';
        Y2 <= '0';
        Y3 <= '1';
        Y4 <= '0';

      when ('1', '1') =>
        Y1 <= '0';
        Y2 <= '0';
        Y3 <= '0';
        Y4 <= '1';

      when others =>
        Y1 <= '0';
        Y2 <= '0';
        Y3 <= '0';
        Y4 <= '0';
    end case;
  end process;

end architecture;

4.对信号十分频?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity DividerBy10 is
  port (
    clk : in std_logic;
    reset : in std_logic;
    divided_clk : out std_logic
  );
end entity;

architecture Behavioral of DividerBy10 is
  signal counter : unsigned(3 downto 0) := (others => '0');
  signal toggle : std_logic := '0';

begin
  process (clk, reset)
  begin
    if reset = '1' then
      counter <= (others => '0');
      toggle <= '0';
    elsif rising_edge(clk) then
      if counter = 9 then
        counter <= (others => '0');
        toggle <= not toggle;
      else
        counter <= counter + 1;
      end if;
    end if;
  end process;

  divided_clk <= toggle;

end architecture;

6.D触发器

library ieee;
use ieee.std_logic_1164.all;

entity DFlipFlop is
  port (
    D, clk, reset : in std_logic;
    Q : out std_logic
  );
end entity;

architecture Behavioral of DFlipFlop is
  signal internal_Q : std_logic := '0';

begin
  process (clk, reset)
  begin
    if reset = '1' then
      internal_Q <= '0';
    elsif rising_edge(clk) then
      internal_Q <= D;
    end if;
  end process;

  Q <= internal_Q;

end architecture;

7.4选1多路开关?

library ieee;
use ieee.std_logic_1164.all;

entity Mux4to1 is
  port (
    S : in std_logic_vector(1 downto 0); -- 选择信号
    D0, D1, D2, D3 : in std_logic;       -- 输入数据
    Y : out std_logic                    -- 输出信号
  );
end entity;

architecture Behavioral of Mux4to1 is
begin
  process (S, D0, D1, D2, D3)
  begin
    case S is
      when "00" =>
        Y <= D0;
      when "01" =>
        Y <= D1;
      when "10" =>
        Y <= D2;
      when "11" =>
        Y <= D3;
      when others =>
        Y <= '0';
    end case;
  end process;

end architecture;

8.移位寄存器?

library ieee;
use ieee.std_logic_1164.all;

entity ShiftRegister4Bit is
  port (
    shift_in : in std_logic;
    shift : in std_logic;
    reset : in std_logic;
    shift_out : out std_logic
  );
end entity;

architecture Behavioral of ShiftRegister4Bit is
  signal register : std_logic_vector(3 downto 0) := (others => '0');
begin
  process (shift_in, shift, reset)
  begin
    if reset = '1' then
      register <= (others => '0');
    elsif rising_edge(shift) then
      if shift = '1' then
        register <= shift_in & register(3 downto 1);
      end if;
    end if;
  end process;

  shift_out <= register(0);

end architecture;

附录:几种常见的数据类型：

STD_LOGIC：有些类似c语言中的bool类型，有0和1两种状态，当然还有别的，就是用得不多

STD_LOGIC_VECTOR：一串01

<=或者=>他代表的不是大于等于，而是箭头，类似于赋值，比如ch<=a,意思就是把a的值赋给ch